The present invention is directed to an apparatus and method for precharging a high-speed memory.
Many applications have a need for high-speed random access memory (RAM), such as dynamic random access memory (DRAM) or static random access memory (SRAM). Such a memory is configured in rows and columns to provide an array of memory cells. Most memories can write or read multi-bit words to or from the memory array by accessing multiple adjacent columns in the memory array simultaneously. Conventional high-speed SRAMs use relatively "narrow" words, e.g., 8 or 16 bits. However, some applications have a need for high-speed memory that can access very wide words, e.g., 128 bits or more. For example, digital signal processors for communications applications need wide words in order to load a full packet of data into a processor module. As another example, high-powered word processing programs with long instructions may need to access data with very wide words.
Unfortunately, wide-word high-speed SRAMs can bum a large amount of power. Specifically, in an SRAM, one bit line for each memory cells being accessed needs to be discharged during each read operation. Since the wide-word SRAMs access a large number of columns simultaneously, a large number of bit lines need to be precharged and discharged for each read operation. Moreover, since the SRAM is operating at high speed, the memory array is being accessed for read operations at high frequencies, and the bit lines need to be precharged and discharged frequently. Due to the frequent read operations and the large number of bit lines that need to be precharged and discharged for each read operation, a conventional high-speed wide-word SRAM can consume a large amount of power. High power consumption can make a chip unsuitable for many battery-powered devices.
One prior art technique to reduce power consumption in SRAMs is to divide the memory array into multiple sections by columns and/or rows. Each section of the memory array is independently prechargeable. During a read operation, only the section of the memory being accessed is precharged. The remaining sections of the memory remain are left uncharged. Unfortunately, breaking the memory array into multiple independently prechargeable sections requires a large number of independent precharge lines and control gates and a large number of sense amplifiers. This increases the physical size (i.e., the required area on the chip) of the memory. In addition, the precharge lines, gates and sense amplifiers require a large number of interconnects, which may not be physically available on the chip.